CS161
Zhu, Justin

CS161 2019-02-14

Thu, Feb 14, 2019
C CS161

Side channels in the microarchitecture. Google Project Zero finds security vulnerabilities, report these vulnerabilities in a responsible fashion. We can have a better OS. Race condition, fetch memory stores in cache and then accesses it from later processes. Virtual memory is defined by PT, PTP, PTW, and PTEU. If PTEU is not set, user process cannot access that page. If user access tries to access a page, then page fault happens.

CS161 2019-02-06

Wed, Feb 6, 2019
C CS161

Proc 1’s page table 300,000 hex. There’s rsp before syscall We want to take interrupts in kernel mode in order for the hardware crash to be handled. Gently click so that hard disk get locked. If interrupts happen in kernel mode, we would have a processor such that the hardware. Magical 5 registers are put on the same stack that it is currently running. We do not call swapgs if the interrupt was not protected in current mode.

CS161 2019-02-05

Tue, Feb 5, 2019
C CS161

Contexts Context switching means changing between different hardware resources. Intentional context switch: System call, which transfers control to the kernel. Traps Unintentional context switch: Interrupt or faults or other exceptions To perform a context switch, we save a state, which saves registers of the old task. Kinds of context Each kernel task context has its own kernel stack, which holds local variables and registers of a task. Question: When the processor is running a kernel task, the %rsp register points into the corresponding stack.

CS161 2019-02-04

Mon, Feb 4, 2019
C CS161

Task Switching How can a processor accomplish more than one task? Time multiplexing or Multitasking We divide the time into slices. It continues to run until we give up the CPU (voluntary context switch) Some hardware device has an urgent message that must be taken care of (involuntary context switch). Timer interrupt is a hardware interrupt, preventing the infinite loop attack! The kernel has full access over the computer’s privileges.